New materials to replace silicon channel will begin what time? Is hard to answer, but some things will definitely happen.

Chip manufacturers are finFET technology transfer by plane to 3D transistors, Intel early in the 2011's has been the transition to 22nm finFET, now has a second-generation finFET14nm, while other generation business also has separately entered 16 / 14nm finFET process battle.

Next generation process technology is very likely tend to 10nm and 7nm finFET structure, but due to limited functionality of silicon material itself may enhance, in order to produce faster chips, may finFET manufacturing process to solve the core parts, namely the channel material .

Channel material facing new challenges

In fact, the chip maker now plans to revise their channel materials, but faces many challenges.

Initially chipmaker concern types of materials, including germanium and III-V compounds, as a channel material 7nm time. Germanium and III-V group elements due to their high electron mobility, can accelerate the movement speed in the channel, and to increase the frequency of the device. However, due to how they are different, germanium and III-V group elements from the process material properties compatible with silicon to become a major challenge.

To this end, the global semiconductor industry is looking for solutions, including silicon germanium for PFET and NFET of strained silicon material. Currently the industry is working, germanium and III-V group elements are under development.

Today, chip manufacturers have been facing a very difficult decision. First, what is the time of transition to the new channel materials, the moment most likely 7nm, it may be time for an exploration of 10nm. Secondly, as the chip maker must have compatible with silicon material processes. The last is to choose between five different candidate materials, including epitaxy, selective epitaxy, wafer bonding, condensation, melting and re-growth.

Next most likely candidate is blank epitaxy (Blank) and selective epitaxy. Because the traditional equipment used to grow epitaxial single-crystal film. ASM International's technical director Ivo Raaijmakers think both methods can be, but what kind of a good hard conclusion.

Lam Research Fellow of Reza Arghavani think epitaxial growth is a slow and complex process, are driving the industry to find alternative methods. Some of these methods may be too costly, there are still under development.

Jumped into the channel material

Has been a hot topic since the channel material this time. A conductive region is a trench MOS device connected between the source and the drain. When a MOSFET transistor is turned on when the gate capacitor voltage is applied to the channel will produce an inversion layer, so that minority carriers between the source and drain through quickly. Otherwise the transistor is turned off.

A major change in the channel material in 90-nanometer process, when the global industry began to introduce strained silicon material. Chip manufacturers use integrated SiGe epitaxial process strained silicon PMOS transistor is formed, or said to make the lattice structure distortion. Thus by increasing the mobility of the hole to achieve increased drive current.

Chip manufacturers may use the same epitaxial process in NMOS 20 nm strained silicon integrated engineering, in order to increase the drive current.

Fellow GlobalFoundries advanced technology structure of Strinivas Banna believed, until today, the challenge has been very clear that in the silicon material used in strained silicon technology has been limited. Especially in the PMOS strain engineering has reached the maximum allowable limits of silicon, but may be a little better in the NMOS.

I believe when the 10nm chip maker 7nm process or channel materials must be changed. In the period of time was considered the first choice is the use of Ge in the PMOS and NMOS used InGaAs material. Because electron mobility Ge up 3,900cm square / Vs, while compared to the silicon material is 1,500cm, InGaAs electron mobility up to 40,000cm square / Vs.

Although mobility higher than Ge and III-V group elements, but are integrated process difficulties, in particular the growth of InGaAs material on silicon material but also a challenge. Banna think different lattice structure of the material is the greatest difficulty. Even for Ge material, the difference in lattice structure is slightly less, but also facing the fundamental question must be grown on germanium oxide layer.

The semiconductor industry is currently looking for a simple way, the chip manufacturer may employ SiGe in the PMOS or 7nm in 10nm, this depends on the company and requirements. For NMOS, more inclined to strained silicon, apparently also using a mixture of Ge. Adam Brand Applied Materials believes that the current data in accordance with the best results SiGe has mass production in the future process nodes IV elements possible incorporation in.

E.g., chip manufacturers must find a suitable mixture ratio of silicon and germanium, using SiGe in the PMOS. Sematech has used 75% and 25% of silicon germanium SiGe base made of PFET, get good results.

But the strained silicon engineering is not simply to find a suitable component of thing, at the beginning of Ge and Si 4% lattice mismatch. Although small lattice mismatch easy process integration, but not much driving current is increased.

Chip manufacturers typically considered to increase the content of Ge in the SiGe mixture may be added in the carrier mobility, but the integration process will be difficult. Further, the use of finFET process may increase the height of the fin, thereby enhancing the driving current. GlobalFoundries of Banna believed in height between the intrinsic strength of the fin material needed to make compromises.

Select the correct process

Future need to find a suitable process to integrate these materials, there are two processes to choose from, a blank (blank) and selective epitaxy. I.e., so-called blank epitaxial epitaxial material over the entire surface, and the other only in the selected area growth surface.

According to expert opinion, both methods require the use of epitaxy equipment, although growing, but slowly. Materials such as Ge channel applications, the amount of output epitaxy equipment is 10-15 per piece. To ensure the quality of growth layer, must use a lower temperature, slow growth, this is not the device itself can solve the problem.

Brand Applied Materials said whether blank or selective epitaxy, channel materials for advanced applications are possible, but if the strain material as SiGE reached 30%, the chip maker more choice would be blank epitaxial growth.

Brand said that in the source / drain and strain engineering applications, selective epitaxy is still the key process steps. Because selective epitaxy process in trenching applications is actually very difficult to achieve.

Blank epitaxy some disadvantages, such as chip manufacturers need to remove the unnecessary portion of the deposited material. Typically chip manufacturers use to pay erosion removed material. Thus, there will be more empty epitaxial process steps, increasing cost.

From such a reason, to get the favor of selective epitaxy. IMEC selective epitaxial growth of III-V and other materials have been used. Selective epitaxy is used in the process finFET structure, but also other mixed material. IMEC's research director, said AaronThean logic devices, and this is the reason they used selective epitaxy process. However, this has also brought other problems, because the effect would be to increase between material defects.

In addition to using epitaxial growth methods outside the industry are looking for the other three methods, wafer bonding, condensation and melting regrowth. But the mainstream is still epitaxial growth. LamResearch of Arghavani believe that all other methods are still being explored, the biggest problem is the cost.

Wafer bonding, including a two-step process, the first chip maker put in a donation silicon surface layer of Ge, however, turn over the silicon layer and the main donor Ge wafers bonded together using epitaxial lift-off process to remove donation layers.

Preparation of silicon with low defect donation is a big challenge. Because there are any defects could be transferred to the device. Arghavani pointed out that today has no method using silicon bonding waferbonding.

Condensation method is mainly used in the PMOS and SOI structure. In the laboratory, IBM has implemented in passing Luofang De 3.3nm finFET strain Ge-on-insulator process. In the condensation method using an epitaxial process in growing a strained SiGe layer on an SOI, wafer at a certain temperature and then condensing process of Ge at the top of the device grown oxide layer, and then the device is subjected to a condensation process again.

Another approach has been the use of selective epitaxy on the patterned silicon substrate Ge epitaxial growth of the channel material, which is at millisecond laser anneal process utilizing Ge melt and re-growth process.

IMEC's Thean that, given the condensation process germanium promising, but the low melting point of germanium, especially in the very next line width in the process of melting and regrowth problem it will spread, which is the problem.

In summary semiconductor industry must carefully 10nm and 7nm from equipment and materials, including a trade-off between performance. Brand Applied Materials that, despite the SiGe epitaxial process and some may temporarily take precedence, but there are still many unknowns. As the chip maker is still exploring a variety of other methods.

From "China Electronics News"